Author(s): Henriques, Ana Isabel Martinho
Date: 2010
Persistent ID: http://hdl.handle.net/10451/4467
Origin: Repositório da Universidade de Lisboa
Subject(s): Engenharia física; Teses de mestrado - 2010
Author(s): Henriques, Ana Isabel Martinho
Date: 2010
Persistent ID: http://hdl.handle.net/10451/4467
Origin: Repositório da Universidade de Lisboa
Subject(s): Engenharia física; Teses de mestrado - 2010
Tese de mestrado, Engenharia Física, Universidade de Lisboa, Faculdade de Ciências, 2010
The trigger logic system of an experimental apparatus is responsible for the data acquisition of that system, i.e., this system decides when data is to be collected. the LAND/ R3B collaboration trigger logic system was updated for the 2010 campaign. In this update the several parts of the trigger system in the different modules were included in one FPGA. This new module so-called VULOM is now responsible for the hole trigger logic and for setting the overall dead time. The FPGA use now implies a 10 ns jitter in the trigger logic signals. This thesis contains the description of the trigger logic system, the old and also the one included in the VULOM. In order to completely understand a experimental setup and the role of the trigger logics, it is necessary to go from the detectors through the conversion of electrical signals to the storage of data. This insight of the electronic setup allowed to start a dead time measurement project. This measurement project main goal is to keep under surveillance the local dead time of the several subsystems. To perform this, it is necessary to keep in mind how the system works and how to synchronize CPU clocks. A plan was outlined and a simulation program was developed to check for its feasibility. Our results suggest that the time required to perform the measurement can be reduced by 30% if the CPU clocks are only corrected with the clocks offset, disregarding the frequency offset. However some simulation improvements are required to further conclusions.