Author(s): Machado, Rui ; Cabral, Jorge ; Alves, Filipe Manuel Serra
Date: 2019
Persistent ID: https://hdl.handle.net/1822/71346
Origin: RepositóriUM - Universidade do Minho
Subject(s): Field-programmable gate-array (FPGA); Nutt-TDC; Synchronization; Time-to-digital converters (TDC)
Applications requiring both high resolution time measurement and large dynamic range demand for the integration of high-performance Time-to-Digital Converters (TDCs) and coarse counting methods which operate asynchronously. When using two asynchronous counting methods, the use of a synchronization mechanism is mandatory to correct metastability errors. Moreover, the placement and routing tools are designed and optimized for synchronous designs, being asynchronous behaviour hard to constraint. Since TDC's principle of operation is based on the asynchronous characteristic of the pulse duration to be measured, this may lead to sub-optimal layouts. In this paper a design methodology for Nutt-TDC synchronizers is presented. The proposed methodology fully solves problems related with automatic placement and routing for proper synchronizer operation. A solution to reduce the critical signals' skew is also proposed along with guidelines on how to define the timing window at which the synchronization must be applied. To validate the proposed methodology a use case implementation of a Nutt-TDC based on a tapped delay line (TDL) is presented. The implemented synchronizer was able to eliminate the existing metastability and synchronization errors validating the efficacy of the proposed methodology.
