Document details

Design of a low-voltage CMOS RF receiver for energy harvesting sensor node

Author(s): Correia, Joana Margarida Coimbra Lamas Pereira

Date: 2014

Persistent ID: http://hdl.handle.net/10362/14721

Origin: Repositório Institucional da UNL

Subject(s): CMOS RF receiver front-end; Low-power; Low-voltage; Wideband balun LNA; Double-balanced passive Mixer; Wireless sensor networks


Description

In this thesis a CMOS low-power and low-voltage RF receiver front-end is presented. The main objective is to design this RF receiver so that it can be powered by a piezoelectric energy harvesting power source, included in a Wireless Sensor Node application. For this type of applications the major requirements are: the low-power and low-voltage operation, the reduced area and cost and the simplicity of the architecture. The system key blocks are the LNA and the mixer, which are studied and optimized with greater detail, achieving a good linearity, a wideband operation and a reduced introduction of noise. A wideband balun LNA with noise and distortion cancelling is designed to work at a 0.6 V supply voltage, in conjunction with a double-balanced passive mixer and subsequent TIA block. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver analog front-end has a total voltage conversion gain of 31.5 dB, a 0.1 - 4.3 GHz bandwidth, an IIP3 value of -1.35 dBm, and a noise figure lower than 9 dB. The total power consumption is 1.9 mW and the die area is 305x134.5 m2, using a standard 130 nm CMOS technology.

Document Type Master thesis
Language English
Advisor(s) Oliveira, Luís
Contributor(s) Correia, Joana Margarida Coimbra Lamas Pereira
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