25 documents found, page 1 of 3
Techniques and Analysis for Mixed-criticality Scheduling with Mode-dependent Se...
Ali Awan, Muhammad; Bletsas, Konstantinos; Souto, Pedro F.; Åkesson, Benny; Tovar, EduardoIn mixed-criticality systems, tasks of different criticality share system resources, mainly to reduce cost. Cost is further reduced by using adaptive mode-based scheduling arrangements, such as Vestal’s model, to improve resource efficiency, while guaranteeing schedulability of critical functionality. To simplify safety certification, servers are often used to provide temporal isolation between tasks. In its si...
Memory Bandwidth Regulation for Multiframe Task Sets
Ali Awan, Muhammad; Souto, Pedro; Bletsas, Konstantinos; Åkesson, Benny; Tovar, EduardoTiming analysis of safety-critical real-time embedded systems should be free of both optimistic and pessimistic aspects. The multiframe model was devised to eliminate the pessimism in the schedulability analysis of systems with tasks whose worst-case execution times vary from job to job, according to known patterns. However, this model is optimistic and unsafe for multicores with shared memory controllers, sinc...
Response time analysis of multiframe mixed-criticality systems
Hussain, Ishfaq; Ali Awan, Muhammad; Souto, Pedro; Bletsas, Konstantinos; Åkesson, Benny; Tovar, EduardoThe well-known model of Vestal aims to avoid excessive pessimism in the quantification of the processing requirements of mixedcriticality systems, while still guaranteeing the timeliness of highercriticality functions. This can bring important savings in system costs, and indirectly help meet size, weight and power constraints. This efficiency is promoted via the use of multiple worst-case execution time (WCET)...
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation
Ali Awan, Muhammad; Bletsas, Konstantinos; Souto, Pedro; Åkesson, Benny; Tovar, EduardoMixed-criticality multicore system design must often provide both safety guarantees and high performance. Memory bandwidth regulation among different cores can be a useful tool for providing safety guarantees as it mitigates the interference when accessing main memory. The use of mode changes and system models such as those of Vestal can help provide both safety, for critical functions, and scheduling performan...
Time-Triggered Co-Scheduling of Computation and Communication with Jitter Requi...
Minaeva, Anna; Åkesson, Benny; Hanzálek, Zdeněk; Dasari, DakshinaThe complexity of embedded application design is increasing with growing user demands. In particular, automotive embedded systems are highly complex in nature, and their functionality is realized by a set of periodic tasks. These tasks may have hard real-time requirements and communicate over an interconnect. The problem is to efficiently co-schedule task execution on cores and message transmission on the inter...
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers
Ali Awan, Muhammad; Souto, Pedro F.; Bletsas, Konstantinos; Åkesson, Benny; Tovar, EduardoIn multicore architectures, there is potential for contention between cores when accessing shared resources, such as system memory. Such contention scenarios are challenging to accurately analyse, from a worst-case timing perspective. One way of making memory contention in multicores more amenable to timing analysis is the use of memory regulation mechanisms. It restricts the number of accesses performed by any...
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controlle...
Awan, Muhammad Ali; Souto, Pedro; Bletsas, Konstantinos; Åkesson, Benny; Tovar, EduardoThis artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task...
Mixed-criticality Scheduling with Memory Bandwidth Regulation
Ali Awan, Muhammad; Souto, Pedro; Bletsas, Konstantinos; Åkesson, Benny; Tovar, EduardoMixed-criticality (MC) multicore system design must reconcile safety guarantees and high performance. The interference among cores on shared resources in such systems leads to unpredictable temporal behaviour. Memory bandwidth regulation among different cores can be a useful tool to mitigate the interference when accessing main memory. However, for mixed-criticality systems conforming to the (well-established) ...
Decoupling Criticality and Importance in Mixed-Criticality Scheduling
Bletsas, Konstantinos; Ali Awan, Muhammad; Souto, Pedro; Åkesson, Benny; Burns, Alan; Tovar, EduardoResearch on mixed-criticality scheduling has flourished since Vestal’s seminal 2007 paper, but more efforts are needed in order to make these results more suitable for industrial adoption and robust and versatile enough to influence the evolution of future certification standards in keeping up with the times. With this in mind, we introduce a more refined task model, in line with the fundamental principles of V...
Uneven memory regulation for scheduling IMA applications on multi-core platforms
Awan, Muhammad Ali; Souto, Pedro; Åkesson, Benny; Bletsas, Konstantinos; Tovar, EduardoThe adoption of multi-cores for mixed-criticality systems has fueled research on techniques for providing scheduling isolation guarantees to applications of different criticalities. These are especially hard to provide in the presence of contention in shared resources of the system, such as buses and DRAMs. The state-of-the-art Single-Core Equivalence (SCE) framework improves timing isolation by enforcing perio...