10 documents found, page 1 of 1
Sub- μW Tow-Thomas Based Biquad Filter with Improved Gain for Biomedical Applic...
Póvoa, R.; Arya, R.; Canelas, A.; Passos, F.; Martins, R.; Lourenço, N.; Horta, N.This paper presents an innovative topology of a gm-C Operational Transconductance Amplifier (OTA), with improved gain and energy-efficiency and its corresponding implementation inside a second order Tow-Thomas based filter configuration, for biomedical and healthcare applications. The proposed OTA architecture takes advantage of a current division technique, as well as the usage of a pair of cross-coupled volta...
A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Eff...
Póvoa, R.; Lourenço, N.; Martins, R.; Canelas, A.; Horta, N.; Goes, J.The topic of this brief is a ingle-stage amplifier biased by a doublet of voltage-combiners in a folded configuration, in order to be supplied by a power source of 1.2 V, maintaining proper dc biasing and voiding the need of any device stacking. The topology has been automatically designed, optimized, and laid out, from sizing to layout level, using a layout-aware approach provided by the AIDA framework, a stat...
Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficie...
Póvoa, R.; Lourenço, N.; Martins, R.; Canelas, A.; Horta, N.; Goes, J.This brief presents the design of a single-stage amplifier with enhanced gain and speed, without the need for using any cascode devices, positive feedback, or feed forward technique. Instead, two voltage-combiners replace the traditional tail current source, commonly employed to bias the differential pair. The resultant topology shows both additional dc gain and a gain bandwidth product enhancement. Simulation ...
Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Cu...
Póvoa, R.; Lourenço, N.; Martins, R.; Canelas, A.; Horta, N.; Goes, J.This brief presents an improved single-stage amplifier biased by voltage-combiners, through the proper usage of current starving. The topology designed and fabricated shows an enhancement of the low-frequency gain, an improvement in the establishing time due to enhanced gain-bandwidth product, and a high improvement of the energy efficiency. The circuit was optimized using AIDA-C, a state-of-the-art multi-objec...
Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC Circuits
Póvoa, R.; Canelas, A.; Martins, R.; Lourenço, N.; Horta, N.; Goes, J.his paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC ...
New Mapping Strategies for Pre-Optimized Inductor Sets in Bottom-Up RF IC Sizin...
Lourenço, N.; Martins, R.; Póvoa, R.; Canelas, A.; Horta, N.; Passos, F.; Castro López, R.; Roca, E.; Fernández, F.This paper presents new indexing and mutation operators, in the context of bottom-up hierarchical multi-objective optimization of radio frequency integrated circuits, for pre-optimized sets of solutions from the hierarchical sub-levels when moving up in hierarchy. Two ideas, one based on a Voronoi decomposition and another based on the nearest neighborhood, are explored, where, and unlike previous approaches th...
Systematic Design of a Voltage Controlled Oscillator using a Layout-Aware Approach
Passos, F.; Castro Lópes, R.; Roca, E.; Fernándes, F.; Martins, R.; Lourenço, N.; Póvoa, R.; Canelas, A.; Horta, N.This paper focuses on the systematic design of voltage controlled oscillators (VCO), a commonly used radiofrequency (RF) electronic circuit. RF circuits are among the most difficult analog circuits to design due to its trade-offs and high operation frequencies. At such operation frequencies, layout parasitics and accurate passive component characterization become of upmost importance, causing re-design iteratio...
Efficient Yield Optimization Method using a Variable K-Means Algorithm for Anal...
Canelas, A.; Martins, R.; Póvoa, R.; Lourenço, N.; Horta, N.This paper presents the study and implementation of a new efficient yield optimization technique for multi-objective optimization-based automatic analog integrated circuit sizing. The approach uses a commercial electrical simulator and standard process design kit (PDK) models to perform, during the optimization process, the same Monte Carlo (MC) simulations that designers use. The proposed yield estimation tech...
Layout-Aware Challenges and a Solution for the Automatic Synthesis of RadioFreq...
Martins, R.; Lourenço, N.; Póvoa, R.; Canelas, A.; Horta, N.; Passos, F.; Castro López, R.; Roca, E.; Fernández, F.In this paper, the major methodologies proposed in the last years to speed-up the synthesis of radio-frequency integrated circuits blocks are overviewed. The challenges to automate this task are discussed, and, to avoid non-systematic iterations between circuit and layout design steps, the architecture of an innovative solution is proposed. The proposed tool exploits the full capabilities of most established co...
Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Sim...
Canelas, A.; Martins, R.; Póvoa, R.; Lourenço, N.; Horta, N.This paper presents an efficient yield optimization approach using k-means clustering algorithm to reduce Monte Carlo (MC) simulations. This approach uses a commercial electrical simulator and PDK models for evaluation purposes. The method was integrated in an analog IC design flow that includes the AIDA-C circuit sizing optimization tool. The proposed yield estimation technique reduces the number of required M...