19 documents found, page 1 of 2

A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Eff...

The topic of this brief is a ingle-stage amplifier biased by a doublet of voltage-combiners in a folded configuration, in order to be supplied by a power source of 1.2 V, maintaining proper dc biasing and voiding the need of any device stacking. The topology has been automatically designed, optimized, and laid out, from sizing to layout level, using a layout-aware approach provided by the AIDA framework, a stat...

A New Family of Cascode-Free Amplifiers with High Energy-Efficiency and Improve...

Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficie...

This brief presents the design of a single-stage amplifier with enhanced gain and speed, without the need for using any cascode devices, positive feedback, or feed forward technique. Instead, two voltage-combiners replace the traditional tail current source, commonly employed to bias the differential pair. The resultant topology shows both additional dc gain and a gain bandwidth product enhancement. Simulation ...

Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Cu...

This brief presents an improved single-stage amplifier biased by voltage-combiners, through the proper usage of current starving. The topology designed and fabricated shows an enhancement of the low-frequency gain, an improvement in the establishing time due to enhanced gain-bandwidth product, and a high improvement of the energy efficiency. The circuit was optimized using AIDA-C, a state-of-the-art multi-objec...

Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC Circuits

his paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC ...

Design of improved rail-to-rail low-distortion and low-stress switches in advan...

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustiv...

A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amp...

15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, Polónia; In this paper a new structure for a multiplying-by-two amplifier is proposed. It is implemented by switching MOS capacitors with floating sources from inversion into depletion dropping the capacitance values in the amplification phase. Low-power is achieved since no operational amplifiers are requir...

New simple digital self-calibration technique for pipeline ADCs using the inter...

IEEE International Symposium on Circuits and Systems, pp. 232 – 235, Seattle, EUA; This paper describes a new digital-domain selfcalibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus. This lowamplitude noise is amplified and recycled by the ADC itself and, due to the successive foldings, it is naturally converted into uniform noise. This noise is then us...

Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based o...

IEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA; This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and s...

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification us...

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA; A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-...