58 documents found, page 1 of 6
Improved memory contention analysis for the 3-Phase task model
Arora, Jatin; Rashid, Syed Aftab; Nelissen, Geoffrey; Maia, Cláudio; Tovar, EduardoIn multiprocessor-based real-time systems, main memory is identified as a major bottleneck in the worst-case timing analysis of tasks. Phased execution models such as the 3-phase task model, i.e., that divides the execution of tasks into distinct computation and memory phases, have shown to be a good candidate to tackle the memory contention problem. The 3-phase execution model in particular has gained much att...
Improved Bus Contention Analysis for 3-Phase Tasks
Arora, Jatin; Rashid, Syed Aftab; Nelissen, Geoffrey; Maia, Cláudio; Tovar, EduardoThe 3-phase task execution model has shown to be a good candidate to tackle the memory bus contention problem. It divides the execution of tasks into computation and memory phases that enable a fine-grained memory bus contention analysis. However, existing works that focus on the bus contention analysis for 3-phase tasks, neglect the fact that memory bus contention strongly relates to the number of bus/memory r...
Memory Contention Analysis for 3-Phase Tasks
Arora, Jatin; Rashid, Syed Aftab; Nelissen, Geoffrey; Maia, Cláudio; Tovar, EduardoIn multiprocessor-based real-time systems, the main memory is identified as the main source of shared resource contention. Phased execution models such as the 3-phase task execution model has shown to be a good candidate to tackle the memory contention problem. It divides the execution of tasks into computation and memory phases that enable a fine-grained memory contention analysis. However, the existing work t...
IPDeN: Real-Time deflection-based NoC with in-order flits delivery
Ribot González, Yilian; Nelissen, Geoffrey; Tovar, EduardoIn deflection-based Network-on-Chips (NoC), when several flits entering a router contend for the same output port, one of the flits is routed to the desired output and the others are deflected to alternatives outputs. The approach reduces power consumption and silicon footprint in comparison to virtual channels (VCs) based solutions. However, due to the nondeterministic number of deflections that flits may suff...
Schedulability Analysis for 3-Phase Tasks with Partitioned Fixed-Priority Sched...
Arora, Jatin; Maia, Cláudio; Rashid, Syed Aftab; Nelissen, Geoffrey; Tovar, EduardoMulticore platforms are being increasingly adopted in Cyber-Physical Systems (CPS) due to their advantages over single-core processors, such as raw computing power and energy efficiency. Typically, multicore platforms use a shared memory bus that connects the cores to the off-chip main memory. This sharing of memory bus may cause tasks running on different cores to compete for access to the main memory whenever...
Work-in-Progress: A Holistic Approach to WCRT Analysis for Multicore Systems
Arora, Jatin; Rashid, Syed Aftab; Maia, Cláudio; Nelissen, Geoffrey; Tovar, EduardoMulticore platforms share the hardware resources such as caches, interconnects, and main memory among all the cores. Due to such sharing, tasks running on different cores compete to access these shared resources which increases the execution times of those tasks in a non-deterministic manner. This is problematic for systems that run applications with stringent timing requirements. To address this issue, we prop...
Bus-Contention Aware WCRT Analysis for the 3-Phase Task Model Considering a Wor...
Arora, Jatin; Maia, Cláudio; Rashid, Syed Aftab; Nelissen, Geoffrey; Tovar, EduardoToday multicore processors are used in most modern systems that require computational logic. However, their applicability in systems with stringent timing requirements is still an ongoing research. This is due to the difficulty of ensuring the timing correctness of tasks executing on a multicore platform that comprises a number of shared hardware resources, e.g., caches, memory bus and the main memory. Concurre...
nDimNoC: Real-Time D-dimensional NoC
Ribot, Yilian; Nelissen, Geoffrey; Tovar, EduardoThe growing demand of powerful embedded systems to perform advanced functionalities led to a large increase in the number of computation nodes integrated in Systems-on-chip (SoC). In this context, network-on-chips (NoCs) emerged as a new standard communication infrastructure for multi-processor SoCs (MPSoCs). In this work, we present nDimNoC, a new D-dimensional NoC that provides real-time guarantees for system...
Tightening the CRPD Bound for Multilevel non- Inclusive Caches
Syed Aftab, Rashid; Nelissen, Geoffrey; Tovar, EduardoTasks running on microprocessors with cache memories are often subjected to cache related preemption delays (CRPDs). CRPDs may significantly increase task execution times, thereby, affecting their schedulability. Schedulability analysis accounting for the impact of CRPD has been extensively studied over the past two decades for systems with a single level of cache. Yet, the literature on CRPD for multilevel non...
Work-In-Progress: WCRT Analysis for the 3-Phase Task Model in Partitioned Sched...
Arora, Jatin; Maia, Cláudio; Rashid, Syed Aftab; Nelissen, Geoffrey; Tovar, EduardoMulticore platforms are being increasingly adopted in Cyber-Physical Systems (CPS) due to their advantages over single-core processors, such as raw computing power and energy efficiency. Typically, multicore platforms use a shared system bus that connects the cores to the memory hierarchy (including caches and main memory). However, such hierarchy causes tasks running on different cores to compete for access to...