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Síntese de circuitos conformes com o standard Boundary Scan

Antunes, Ana; Marzouki, Meryem; Ferrari, António

This paper presents a tool that allows the inclusion of the Boundary Scan test logic in a VHDL description of a given integrated circuit.; Este artigo apresenta uma ferramenta que permite a inclusão de facilidades de teste ao nível da descrição VHDL de um circuito integrado. A lógica de teste incluida respeita o standard Boundary Scan.

Date: 1996   |   Origin: Electrónica e Telecomunicações
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Geração de vectores de teste por emparelhamento

Dias, Fernando Morgado; Touati, Mohamed Hedi; Marzouki, Meryem; Ferrari, António

This paper presents a method to generate test vectors for an electronic board composed of modules from which the structural description it’s not known. The only information available is the set of test vectors, their coverage on the primary inputs and outputs of each module provided by the manufacturer and the composition of the board. This method provides test vectors to test the board from its primary inputs ...

Date: 1996   |   Origin: Electrónica e Telecomunicações
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