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Design and characterization of a 20 Gbit/s clock recovery circuit

Monteiro, P.; Matos, J. N.; Gameiro, A.; Matos, P. A.; Rocha, J. F. da

In this communication we report the design of a clock recovery circuit produced for the 20 Gbit/s demonstrator of the RACE 2011 project "TRAVEL" of the European Community. The clock recovery circuit is based on an open loop structure using a dielectric resonator narrow bandpass filter with high Q. A detailed electrical characterization of the circuit and alsoits sensitivity to temperature and detuning variation...

Date: 1995   |   Origin: Electrónica e Telecomunicações
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