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Extensive Analysis of a Real-Time Dense Wired Sensor Network Based on Traffic S...

Loureiro, João; Rangarajan, Raghuraman; Nikolic, Borislav; Soares Indrusiak, Leandro; Tovar, Eduardo

XDense is a novel wired 2D mesh grid sensor network system for application scenarios that benefit from densely deployed sensing (e.g., thousands of sensors per square meter). It was conceived for cyber-physical systems that require real-time sensing and actuation, like active flow control on aircraft wing surfaces. XDense communication and distributed processing capabilities are designed to enable complex featu...


Buffer-aware bounds to multi-point progressive blocking in priority-preemptive ...

Indrusiak, Leandro; Burns, Alan; Nikolic, Borislav

This paper aims to reduce the pessimism of the analysis of the multi-point progressive blocking (MPB) problem in real-time priority-preemptive wormhole networks-on-chip. It shows that the amount of buffering on each network node can influence the worst-case interference that packets can suffer along their routes, and it proposes a novel analytical model that can quantify such interference as a function of the b...


Real-Time Dense Wired Sensor Network Based on Traffic Shaping

Loureiro, João; Rangarajan, Raghuraman; Nikolic, Borislav; Indrusiak, Leandro; Tovar, Eduardo

XDense is a novel wired 2D-mesh grid sensor network system for application scenarios that benefit from densely deployed sensing (e.g. thousands of sensors per square meter). It was conceived for closed-loop cyber-physical systems (CPS) that require real-time actuation, like active flow control (AFC) on aircraft wing surfaces. XDense communication and distributed processing capabilities are designed such that th...


Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Becker, Matthias; Nikolic, Borislav; Dasari, Dakshina; Åkesson, Benny; Nélis, Vincent; Behnam, Moris; Nolte, Thomas

Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip, which is used for communication among the compute cores via the offchi...


Optimal Minimal Routing and Priority Assignment for Priority-Preemptive Real-Ti...

Nikolic, Borislav; Pinho, Luís Miguel

The Network-on-Chip (NoC) architecture is an interconnect network with a good performance and scalability potential. Thus, it comes as no surprise that NoCs are among the most popular interconnect mediums in nowadays available many-core platforms. Over the years, the real-time community has been attempting to make NoCs amenable to the real-time analysis. One such approach advocates to employ virtual channels. V...


Contention-Free Execution of Automotive Applications on a Clustered Many-Core P...

Becker, Matthias; Dasari, Dakshina; Nikolic, Borislav; Åkesson, Benny; Nelis, Vincent; Nolte, Thomas

Next generations of compute-intensive real-time applications in automotive systems will require more powerful computing platforms. One promising power-efficient solution for such applications is to use clustered many-core architectures. However, ensuring that real-time requirements are satisfied in the presence of contention in shared resources, such as memories, remains an open issue. This work presents a nove...


Worst-Case Communication Delay Analysis for NoC-Based Many-Cores Using a Limite...

Nikolic, Borislav; Yomsi, Patrick Meumeu; Petters, Stefan M.

A steady increase in the number of cores within many-core platforms causes increasing contentions for the interconnect medium and leads to non-negligible latencies of the inter-core communication. In order to study the worst-case execution times of applications, it is no longer sufficient to only take into account their schedulability requirements, but the communication delays also have to be considered. In thi...


On Routing Flexibility of Wormhole-Switched Priority-Preemptive NoCs

Nikolic, Borislav; Pinho, Luís Miguel; Indrusiak, Leandro

Flit-level preemptions via virtual channels have been proposed as one viable method to implement prioritypreemptive arbitration policies in NoC routers, and integrate NoCs in the hard real-time domain. In recent years, researchers have explored several aspects of priority-preemptive NoCs, such as different arbitration techniques, different priority assignment methods (where applicable) and different workload ma...


Towards realistic core-failure-resilient scheduling and analysis

Nikolic, Borislav; Bletsas, Konstantinos

On uniprocessors, a failure of the single core means unavoidable system failure. However, on multicores, when a core fails, it is conceivable that the computation could continue on remaining cores in a degraded system mode indefinitely, until orderly shutdown and servicing can take place. This would be very desirable for critical applications but, apart from hardware and software support, it would require (i) a...


Hard real-time multiprocessor scheduling resilient to core failures

Nikolic, Borislav; Bletsas, Konstantinos; M. Petters, Stefan

Most multiprocessor scheduling theory overlooks the possibility of hardware failures that entirely nullify the computation carried out by a task instance, and potentially also make the respective processor henceforth unusable. Yet, such failures may occur, causing the system to fail. Motivated by this reality, we introduce a new concept of hard real-time schedulability guarantees for critical multiprocessor sys...


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