The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. Ho...
Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection ca...
Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure...
Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanism...
Chip debug infrastructures, present in most recent microprocessors, to execute real time fault injection campaigns. It is based on a debugger customized for fault injection and designed for maximum performance and flexibility. The developed methodology can be applied on the verification of dependable systems.
This paper presents a set of modifications to common processor on-chip debugging infrastructures to support the execution of fault injection campaigns. The proposed solution is applicable to different target architectures and imposes a very low logic overhead, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.