Detalhes do Documento

Multilevel inverters have been widely used in power electronics as a viable and effective alternative to conventional two-level converters in high-voltage system applications. Among the advantages of these topologies, we highlight the reduction of effort on the switches, as well as the total harmonic distortion (THD), enabling the reduction of magnetic components. This work had the purpose of implementing and evaluating a space vector pulse width modulation (SVPWM) technique for a three-phase neutral-point diode-clamped (NPC) multilevel inverter controlled by FPGA. The proposed system consists of an Intel FPGA kit using the MAX 10 family connected to a prototype board developed with the NPC inverter. This board was designed with a diode full-bridge rectifier, capacitive voltage divider of the direct current bus, gate drivers for the safe operation of the 12 MOSFET switches and 6 clamp diodes, in addition to the input, output and power connectors. The command strategy is based on the transformation of the three-phase system into coordinates by the Clarke transform, calculation of the switching times of the vectors of each group of subsectors and definition of the activation times of the switches of each arm of the inverter. For this purpose, three reference sine waves with frequency of 60 Hz phase lag of 120° and a triangular carrier with a switching frequency of 2520 Hz were used. After simulating and validating the SVPWM algorithm to control the NPC topology with the Power Simtech software (PSIM), the synthesis and simulation of hardware description codes in VHDL language were performed with the softwares Quartus Prime and ModelSim Altera, respectively. The transformation strategy in orthogonal coordinates with sectors and sub-sectors of operation proved to be efficient, allowing spatial simplifications that reduced both the computational cost and hardware resources of the FPGA. The simulated and experimental results are presented for the amplitude modulation indices of 1.15 (100%), 1.04 (90%), 0.92 (80%), 0.81 (70%) and 0.69 (60%) in empty and loaded conditions for a total output power of approximately 1000 W. Additionally, experimental comparisons of the THD of the 5-level line voltage generated by the sinusoidal PWM (SPWM) and SVPWM are shown. Considering the maximum modulation index, the THDs obtained in the experimental tests without load for the SPWM and SVPWM techniques, were 35.31% and 29.94%, respectively, and with load, 37.72% and 28.44%, respectively. The qualitative analyzes of the phase and line waveforms generated by the proposed system, and the quantitative ones of THD evaluations, corroborate the perfect functioning of the implemented algorithms and prototype, showing that the presented methodology can be explored in teaching and research activities at undergraduate and graduate levels.

Multilevel inverters have been widely used in power electronics as a viable and effective alternative to conventional two-level converters in high-voltage system applications. Among the advantages of these topologies, we highlight the reduction of effort on the switches, as well as the total harmonic distortion (THD), enabling the reduction of magnetic components. This work had the purpose of implementing and evaluating a space vector pulse width modulation (SVPWM) technique for a three-phase neutral-point diode-clamped (NPC) multilevel inverter controlled by FPGA. The proposed system consists of an Intel FPGA kit using the MAX 10 family connected to a prototype board developed with the NPC inverter. This board was designed with a diode full-bridge rectifier, capacitive voltage divider of the direct current bus, gate drivers for the safe operation of the 12 MOSFET switches and 6 clamp diodes, in addition to the input, output and power connectors. The command strategy is based on the transformation of the three-phase system into coordinates by the Clarke transform, calculation of the switching times of the vectors of each group of subsectors and definition of the activation times of the switches of each arm of the inverter. For this purpose, three reference sine waves with frequency of 60 Hz phase lag of 120° and a triangular carrier with a switching frequency of 2520 Hz were used. After simulating and validating the SVPWM algorithm to control the NPC topology with the Power Simtech software (PSIM), the synthesis and simulation of hardware description codes in VHDL language were performed with the softwares Quartus Prime and ModelSim Altera, respectively. The transformation strategy in orthogonal coordinates with sectors and sub-sectors of operation proved to be efficient, allowing spatial simplifications that reduced both the computational cost and hardware resources of the FPGA. The simulated and experimental results are presented for the amplitude modulation indices of 1.15 (100%), 1.04 (90%), 0.92 (80%), 0.81 (70%) and 0.69 (60%) in empty and loaded conditions for a total output power of approximately 1000 W. Additionally, experimental comparisons of the THD of the 5-level line voltage generated by the sinusoidal PWM (SPWM) and SVPWM are shown. Considering the maximum modulation index, the THDs obtained in the experimental tests without load for the SPWM and SVPWM techniques, were 35.31% and 29.94%, respectively, and with load, 37.72% and 28.44%, respectively. The qualitative analyzes of the phase and line waveforms generated by the proposed system, and the quantitative ones of THD evaluations, corroborate the perfect functioning of the implemented algorithms and prototype, showing that the presented methodology can be explored in teaching and research activities at undergraduate and graduate levels.