Publicação

RISC-V Virtualization for a CVA6-based SoC

Detalhes bibliográficos
Resumo:	In this work, we describe the implementation of the latest version of the RISC-V Hypervisor extension (v1.0) specification in a RISC-V CVA6-based (64-bit) SoC. We also report the results of performing an extensive evaluation on the current design and we share our experience about the design space exploration for a few microarchitectural optimizations to the memory subsystem. To complete, we have also enhanced the timer infrastructure by implementing the privileged timer Sstc extension. All these efforts we conducted in an attempt to improve performance without compromising area and power.
Autores principais:	Sá, Bruno Vilaça
Outros Autores:	Valente, Luca; Martins, José Carvalho; Rossi, Davide; Benini, Luca; Pinto, Sandro
Assunto:	Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática Indústria, inovação e infraestruturas
Ano:	2022
País:	Portugal
Tipo de documento:	póster em conferência
Tipo de acesso:	acesso aberto
Instituição associada:	Universidade do Minho
Idioma:	inglês
Origem:	RepositóriUM - Universidade do Minho

Descrição
Resumo:	In this work, we describe the implementation of the latest version of the RISC-V Hypervisor extension (v1.0) specification in a RISC-V CVA6-based (64-bit) SoC. We also report the results of performing an extensive evaluation on the current design and we share our experience about the design space exploration for a few microarchitectural optimizations to the memory subsystem. To complete, we have also enhanced the timer infrastructure by implementing the privileged timer Sstc extension. All these efforts we conducted in an attempt to improve performance without compromising area and power.