Publicação
HACC-V: hardware-assisted cryptographic coprocessor for RISC-V
| Resumo: | Embedded systems have shown a remarkable evolution in recent years, driven by their widespread utilization in solutions for the Internet of Things (IoT). These devices, traditionally known for their low power consumption and high resource scarcity, are now starting to offer more robust solutions not only in terms of performance, but also in terms of connectivity and security. Regarding the latter, many current security mechanisms resort to cryptographic algorithms to protect point-to-point communication, which, despite being a well-studied requirement in traditional networks, implies new challenges when addressed in embedded systems connected to the Internet. However, the use of cryptographic protocols, such as Advanced Encryption Standard (AES), to ensure connectivity security in low-resource IoT devices requires extra processing capabilities. For this reason, hardware solutions capable of accelerating and optimizing these algorithms have already been developed. This dissertation aims at developing HACC-V, a cryptographic coprocessor for reconfigurable IoT de vices designed to provide hardware acceleration to network layers that demand communication security and use protocols based on AES. The solution is deployed on a reconfigurable low-end platform with Field Programmable Gate Array (FPGA), and by taking advantage of the RISC-V Instruction Set Architecture (ISA), the accelerator is implemented and studied following two distinct coupling approaches: tightly-coupled and loosely-coupled. Moreover, this dissertation developed an Application Programming Interface (API) to pro vide an agnostic abstraction layer, enabling any IoT operating system (OS) to use the coprocessor. In order to evaluate the developed work, the performed experiments have compared the software-based AES setup with the proposed hardware-based solution (HACC-V) with both the tightly- and loosely-coupled approaches. Additionally, the Thread-Metrics Benchmark was performed to evaluate the OS performance in a typical IoT setup. The results reveal that HACC-V achieves better performance metrics than the native solutions, which contributed to increase the performance availability of the OS in the IoT. Furthermore, the analysis of both coupling approaches led to the conclusion that the tightly-coupled approach provided better performance and determinism than the loosely-coupled approach. |
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| Autores principais: | Sousa, Pedro |
| Assunto: | Embedded systems IoT FPGA AES Cryptographic coprocessor Sistemas embebidos Coprocessador criptográfico Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática |
| Ano: | 2022 |
| País: | Portugal |
| Tipo de documento: | dissertação de mestrado |
| Tipo de acesso: | acesso aberto |
| Instituição associada: | Universidade do Minho |
| Idioma: | inglês |
| Origem: | RepositóriUM - Universidade do Minho |
| Resumo: | Embedded systems have shown a remarkable evolution in recent years, driven by their widespread utilization in solutions for the Internet of Things (IoT). These devices, traditionally known for their low power consumption and high resource scarcity, are now starting to offer more robust solutions not only in terms of performance, but also in terms of connectivity and security. Regarding the latter, many current security mechanisms resort to cryptographic algorithms to protect point-to-point communication, which, despite being a well-studied requirement in traditional networks, implies new challenges when addressed in embedded systems connected to the Internet. However, the use of cryptographic protocols, such as Advanced Encryption Standard (AES), to ensure connectivity security in low-resource IoT devices requires extra processing capabilities. For this reason, hardware solutions capable of accelerating and optimizing these algorithms have already been developed. This dissertation aims at developing HACC-V, a cryptographic coprocessor for reconfigurable IoT de vices designed to provide hardware acceleration to network layers that demand communication security and use protocols based on AES. The solution is deployed on a reconfigurable low-end platform with Field Programmable Gate Array (FPGA), and by taking advantage of the RISC-V Instruction Set Architecture (ISA), the accelerator is implemented and studied following two distinct coupling approaches: tightly-coupled and loosely-coupled. Moreover, this dissertation developed an Application Programming Interface (API) to pro vide an agnostic abstraction layer, enabling any IoT operating system (OS) to use the coprocessor. In order to evaluate the developed work, the performed experiments have compared the software-based AES setup with the proposed hardware-based solution (HACC-V) with both the tightly- and loosely-coupled approaches. Additionally, the Thread-Metrics Benchmark was performed to evaluate the OS performance in a typical IoT setup. The results reveal that HACC-V achieves better performance metrics than the native solutions, which contributed to increase the performance availability of the OS in the IoT. Furthermore, the analysis of both coupling approaches led to the conclusion that the tightly-coupled approach provided better performance and determinism than the loosely-coupled approach. |
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