Autor(es): Martins, R. ; Lourenço, N. ; Póvoa, R. ; Canelas, A. ; Horta, N. ; Passos, F. ; Castro López, R. ; Roca, E. ; Fernández, F.
Data: 2017
Identificador Persistente: http://hdl.handle.net/10400.26/54470
Origem: Escola Superior Náutica Infante D. Henrique
In this paper, the major methodologies proposed in the last years to speed-up the synthesis of radio-frequency integrated circuits blocks are overviewed. The challenges to automate this task are discussed, and, to avoid non-systematic iterations between circuit and layout design steps, the architecture of an innovative solution is proposed. The proposed tool exploits the full capabilities of most established computer-aided design tools available nowadays, i.e., off-the-shelf circuit simulator, electromagnetic simulator and layout extractor. The approach intends to bypass the two major bottlenecks of RF-design: the design of reliable integrated inductors and accurate layout parasitic estimates since the early stages of design process.
