Author(s): Agopian, P. G. D. [UNESP] ; Bordallo, C. ; Martino, J. A. ; Rooyackers, R. ; Simoen, E. ; Collaert, N. ; Claeys, C. ; Huang, R. ; Wu, H. ; Lin, Q. ; Liang, S. ; Song, P. L. ; Guo, Z. ; Lai, K. ; Zhang, Y. ; Wang, Y. ; Shi, Y. ; Lung, H. L.
Date: 2022
Persistent ID: http://hdl.handle.net/11449/218327
Origin: Oasisbr
Subject(s): TFET; geometries; new materials; digital and analog performance
Made available in DSpace on 2022-04-28T17:20:27Z (GMT). No. of bitstreams: 0 Previous issue date: 2018-01-01
Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
imec's Logic Device Program and its Core Partners
Different Tunnel-FET technologies are analyzed in terms of digital and analog figures of merit. The digital figure of merit used was the subthreshold swing (SS), while the analog parameter was the intrinsic voltage gain (AV). In the early technologies based on silicon TFET devices, the SS was much higher than the ideal behavior. However, the Av was very good, reaching a value up to 80 dB. The opposite trends were observed for up to date technologies based on III-V materials, where the SS finally reaches values down to 60 mV/dec while the AV degrades to 32 dB. The explanation is related to the predominant conduction mechanism. In the III-V TFETs, Band to Band (B2B) Tunneling is the predominant mechanism, which is more sensible to the drain electric field, increasing the output conductance and degrading the AV. In the silicon based TFETs the Trap-Assisted-Tunneling (TAT) is the predominant mechanism, which is less dependent on the drain electric field, resulting in a better AV.
Univ Sao Paulo, LSI PSI USP, Sao Paulo, Brazil
Sao Paulo State Univ, UNESP, Campus Sao Joao da Boa Vista, Sao Paulo, Brazil
IMEC, Leuven, Belgium
Katholieke Univ Leuven, EE Dept, Leuven, Belgium
Sao Paulo State Univ, UNESP, Campus Sao Joao da Boa Vista, Sao Paulo, Brazil
