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Estimation of WCET using a little language to describe microcontrollers and DSPs architectures

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Detalhes bibliográficos
Resumo:A method for analysing and predicting the timing properties of a program fragment will be described. First a little language implemented to describe a processor’s architecture is presented followed by the presentation of a new static WCET estimation method. The timing analysis starts by compiling a processor’s architecture program followed by the disassembling of the program fragment. After sectioning the assembler program into basic blocks call graphs are generated and these data are later used to evaluate the pipeline hazards and cache miss that penalize the real-time performance. Some experimental results of using the developed tool to predict the WCET of code segments using some Intel microcontroller are presented. Finally, some conclusions and future work are presented.
Autores principais:Tavares, Adriano
Outros Autores:Couto, Carlos
Assunto:WCET estimation Call graph Little language Basic block
Ano:2001
País:Portugal
Tipo de documento:comunicação em conferência
Tipo de acesso:acesso aberto
Instituição associada:Universidade do Minho
Idioma:inglês
Origem:RepositóriUM - Universidade do Minho
Descrição
Resumo:A method for analysing and predicting the timing properties of a program fragment will be described. First a little language implemented to describe a processor’s architecture is presented followed by the presentation of a new static WCET estimation method. The timing analysis starts by compiling a processor’s architecture program followed by the disassembling of the program fragment. After sectioning the assembler program into basic blocks call graphs are generated and these data are later used to evaluate the pipeline hazards and cache miss that penalize the real-time performance. Some experimental results of using the developed tool to predict the WCET of code segments using some Intel microcontroller are presented. Finally, some conclusions and future work are presented.