Publicação
STUDY AND DESIGN OF A DIGITALLY CONTROLLED OSCILLATOR (DCO) FOR ALL-DIGITAL PLL
| Resumo: | The work presented in this dissertation focuses on the study and design of a Digitally Controlled Oscillator (DCO) architecture for integration within an All Digital Phased Locked Loop (ADPLL). The digital nature of the proposed DCO facilitates its implementa- tion using standard digital cells, enabling integration into Sytem on Chip (SoC) solutions, particularly for low-power transceiver applications. The proposed DCO, implemented in 65nm CMOS technology, uses configurable inverter stages controlled by a bias current cell, which is tunable via a digital input. Two versions of the DCO were developed: one targeting the Sub-1GHz frequency bands for Short-Range Device (SRD) applications, and the other designed for the 2.4 GHz ISM band. The designed DCO achieves frequency tuning ranges of 863.14–870.64 MHz and 2.4–2.495 GHz, with corresponding phase noise performance of -95.04 dBc/Hz and -80.04 dBc/Hz at a 1 MHz offset. In terms of power consumption, the bias current cells controlling the Ring Oscillators (ROs) consume between 1.047–1.098 mW (Sub-1GHz DCO) and 874.3–965.8 W (2.4 GHz DCO). Finally, the complete Voltage-Controlled Oscillators (VCOs) implementations incorpo- rating the Digitally Controlled Oscillators (DCOs) exhibit power consumptions ranging from 109.5–110.4 W (Sub-1GHz) and 87.17–90.96 W (2.4 GHz ISM band). |
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| Autores principais: | Ferreira, Rafael José Fonseca |
| Assunto: | Digitally Controlled Oscillator (DCO) Hardware Description Languages (HDL) Phase Locked Loop (PLL) Short-Range Device (SRD) ing Oscillator (RO) Voltage-Controlled Oscillator (VCO) |
| Ano: | 2025 |
| País: | Portugal |
| Tipo de documento: | dissertação de mestrado |
| Tipo de acesso: | acesso aberto |
| Instituição associada: | Universidade Nova de Lisboa |
| Idioma: | inglês |
| Origem: | Repositório Institucional da UNL |
| Resumo: | The work presented in this dissertation focuses on the study and design of a Digitally Controlled Oscillator (DCO) architecture for integration within an All Digital Phased Locked Loop (ADPLL). The digital nature of the proposed DCO facilitates its implementa- tion using standard digital cells, enabling integration into Sytem on Chip (SoC) solutions, particularly for low-power transceiver applications. The proposed DCO, implemented in 65nm CMOS technology, uses configurable inverter stages controlled by a bias current cell, which is tunable via a digital input. Two versions of the DCO were developed: one targeting the Sub-1GHz frequency bands for Short-Range Device (SRD) applications, and the other designed for the 2.4 GHz ISM band. The designed DCO achieves frequency tuning ranges of 863.14–870.64 MHz and 2.4–2.495 GHz, with corresponding phase noise performance of -95.04 dBc/Hz and -80.04 dBc/Hz at a 1 MHz offset. In terms of power consumption, the bias current cells controlling the Ring Oscillators (ROs) consume between 1.047–1.098 mW (Sub-1GHz DCO) and 874.3–965.8 W (2.4 GHz DCO). Finally, the complete Voltage-Controlled Oscillators (VCOs) implementations incorpo- rating the Digitally Controlled Oscillators (DCOs) exhibit power consumptions ranging from 109.5–110.4 W (Sub-1GHz) and 87.17–90.96 W (2.4 GHz ISM band). |
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