Publicação
Ultra Low Power Clock and Data Recovery System for In-Vivo sensing devices
| Resumo: | Sensible surgeries (to organs such as the heart or the brain) benefit from a system that provides real time precise information of the pose of the surgical tools in relation to the tissue that is being operated. For that, the MCCI investigation group, working in Tyndall National Institute, is developing an in-vivo sensing capable of calculating its pose on a relative coordinate system. The means by which its pose is calculated is by processing the amplitude of incoming signals. This implies the necessity of a Data collection system (which needs to be clocked). Reference Quartz oscillators are too big for such miniature devices, thus a Clock Recovery System needs to be developed, which is the aim of this project. After analyzing the characteristics of the input signal, a clock signal was extracted from it (through a set of non-linear operations). This clock is then used as a reference to a digital PLL (digital filter phase-locked loop), that generates an output frequency that is 32 times bigger than its reference. The structure is composed of an 8 bits Gated Ring Oscillator Time to Digital Converter (GRO-TDC) with a time resolution of 1.22s, a PI digital filter with a proportional gain of 1 and an integral gain of 1 8 , and a Current Starved Ring Oscillator that is controlled by a 9 bits I-DAC (achieving a frequency resolution of 100Hz). One of the main challenges of this design is related with the frequency of the reference clock, which is extremely low (3.2kHz) – making it difficult to conciliate the attenuation of the phase noise of the reference clock with the other sources of phase noise (such as the oscillator). Some distinct features of this structure is that the digital PLL is combined with a block that detects the absence of the reference clock disconnecting the DPLL in that scenario (to avoid the structure drifting away from lock) and an instant phase locking mechanism, that instantly locks the phase of the feedback clock once the reference signal is back. These blocks increase the performance of the system – once the PLL locks to the reference signal it never looses (phase and frequency) lock. The generated clock has an absolute jitter of 470ns and a 32 period jitter of 490ns for the typical process corner case. However, this performance is significantly impacted by process corners, leading to a worse case scenario of 4.22s of absolute jitter and a 32 period jitter (the absolute jitter of the sampling clock – that has a period of 312.5s) of 4.28s. A solution for this problem was proposed as a future work perspective. The circuit was implemented in a technology of 180nm (XT018 from XFAB), with a power supply of 1.2V, resulting in a consumption of 6 W and a total area of 0.1mm2. |
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| Autores principais: | Cortez, Tiago Filipe Fernandes |
| Assunto: | All digital PLL Digital Filter PLL Low Power Clock and Data Recovery System CDR Clock Recovery System |
| Ano: | 2024 |
| País: | Portugal |
| Tipo de documento: | dissertação de mestrado |
| Tipo de acesso: | acesso aberto |
| Instituição associada: | Universidade Nova de Lisboa |
| Idioma: | inglês |
| Origem: | Repositório Institucional da UNL |
| Resumo: | Sensible surgeries (to organs such as the heart or the brain) benefit from a system that provides real time precise information of the pose of the surgical tools in relation to the tissue that is being operated. For that, the MCCI investigation group, working in Tyndall National Institute, is developing an in-vivo sensing capable of calculating its pose on a relative coordinate system. The means by which its pose is calculated is by processing the amplitude of incoming signals. This implies the necessity of a Data collection system (which needs to be clocked). Reference Quartz oscillators are too big for such miniature devices, thus a Clock Recovery System needs to be developed, which is the aim of this project. After analyzing the characteristics of the input signal, a clock signal was extracted from it (through a set of non-linear operations). This clock is then used as a reference to a digital PLL (digital filter phase-locked loop), that generates an output frequency that is 32 times bigger than its reference. The structure is composed of an 8 bits Gated Ring Oscillator Time to Digital Converter (GRO-TDC) with a time resolution of 1.22s, a PI digital filter with a proportional gain of 1 and an integral gain of 1 8 , and a Current Starved Ring Oscillator that is controlled by a 9 bits I-DAC (achieving a frequency resolution of 100Hz). One of the main challenges of this design is related with the frequency of the reference clock, which is extremely low (3.2kHz) – making it difficult to conciliate the attenuation of the phase noise of the reference clock with the other sources of phase noise (such as the oscillator). Some distinct features of this structure is that the digital PLL is combined with a block that detects the absence of the reference clock disconnecting the DPLL in that scenario (to avoid the structure drifting away from lock) and an instant phase locking mechanism, that instantly locks the phase of the feedback clock once the reference signal is back. These blocks increase the performance of the system – once the PLL locks to the reference signal it never looses (phase and frequency) lock. The generated clock has an absolute jitter of 470ns and a 32 period jitter of 490ns for the typical process corner case. However, this performance is significantly impacted by process corners, leading to a worse case scenario of 4.22s of absolute jitter and a 32 period jitter (the absolute jitter of the sampling clock – that has a period of 312.5s) of 4.28s. A solution for this problem was proposed as a future work perspective. The circuit was implemented in a technology of 180nm (XT018 from XFAB), with a power supply of 1.2V, resulting in a consumption of 6 W and a total area of 0.1mm2. |
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