Publicação
Study of a Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators
| Resumo: | In modern electronics systems there has been a great push to have a constant size re- duction of Complementary Metal-Oxide-Semiconductor (CMOS) technologies which can have different consequences, such as a reduction of the intrinsic gain of CMOS transistors and an increase of their transition frequency. This has resulted in increasing the difficulty of designing high gain, high bandwidth low power amplifiers. This can be a problem when designing high performance Sigma-Delta Modulators (Σ∆Ms). Recently, it was pro- posed to use active-passive Σ∆Ms architectures, where the loop gain is mainly obtained from the comparators processing gain, thus reducing the gain required for the amplifiers. Multi-stAge Noise SHaping (MASH) structures present a stable alternative to high-order single-loop typologies. Nevertheless, typically, these are very sensitive to the analog cir- cuit imperfections, since their performance relies on the accuracy of the values of the analog circuit’s transfer functions matching with the coefficients in the Digital Cancella- tion Logic (DCL) in order to avoid noise leakage and achieve their desired performance. This is the case with the passive 2-1 MASH Σ∆M developed based on [1], which has it’s performance limited by process variations of the values of it’s constituted components. In the used CMOS technology, process variations can cause the R · C value to change up to 37%, which causes mismatch between the Σ∆M analog transfer functions and the DCL transfer functions and also causes a variation in the overloading voltage of the modulator. Both these issues can cause degradation in Signal-to-Noise-and-Distortion Ratio (SNDR) of the modulator. In order to solve these problems, this thesis proposes a circuit capable of measuring the value of RC TS and then using this value to calibrate the coefficients in the DCL to match the analog transfer functions and adjust the reference voltage (Vref ) in order to reduce the variation of the Σ∆M overload voltage. In order to validate the calibration concept, the performance of 2-1 MASH Σ∆M implemented with and without calibration was analyzed by performing process, voltage and temperature (PVT) corners and Monte Carlo simulations. The results show that by implementing the calibration it was possible to reduce the variability of the SNDR results, as well as increase worst corners results. |
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| Autores principais: | Brito, Inês Ferreira Casaleiro Nogueira de |
| Assunto: | Analog to Digital Converter (ADC) Sigma-Delta Modulators (Σ∆Ms) 2-1 MASH Σ∆M Passive Integrators RC Time Constant Calibration RC Time Constant |
| Ano: | 2023 |
| País: | Portugal |
| Tipo de documento: | dissertação de mestrado |
| Tipo de acesso: | acesso aberto |
| Instituição associada: | Universidade Nova de Lisboa |
| Idioma: | inglês |
| Origem: | Repositório Institucional da UNL |
| Resumo: | In modern electronics systems there has been a great push to have a constant size re- duction of Complementary Metal-Oxide-Semiconductor (CMOS) technologies which can have different consequences, such as a reduction of the intrinsic gain of CMOS transistors and an increase of their transition frequency. This has resulted in increasing the difficulty of designing high gain, high bandwidth low power amplifiers. This can be a problem when designing high performance Sigma-Delta Modulators (Σ∆Ms). Recently, it was pro- posed to use active-passive Σ∆Ms architectures, where the loop gain is mainly obtained from the comparators processing gain, thus reducing the gain required for the amplifiers. Multi-stAge Noise SHaping (MASH) structures present a stable alternative to high-order single-loop typologies. Nevertheless, typically, these are very sensitive to the analog cir- cuit imperfections, since their performance relies on the accuracy of the values of the analog circuit’s transfer functions matching with the coefficients in the Digital Cancella- tion Logic (DCL) in order to avoid noise leakage and achieve their desired performance. This is the case with the passive 2-1 MASH Σ∆M developed based on [1], which has it’s performance limited by process variations of the values of it’s constituted components. In the used CMOS technology, process variations can cause the R · C value to change up to 37%, which causes mismatch between the Σ∆M analog transfer functions and the DCL transfer functions and also causes a variation in the overloading voltage of the modulator. Both these issues can cause degradation in Signal-to-Noise-and-Distortion Ratio (SNDR) of the modulator. In order to solve these problems, this thesis proposes a circuit capable of measuring the value of RC TS and then using this value to calibrate the coefficients in the DCL to match the analog transfer functions and adjust the reference voltage (Vref ) in order to reduce the variation of the Σ∆M overload voltage. In order to validate the calibration concept, the performance of 2-1 MASH Σ∆M implemented with and without calibration was analyzed by performing process, voltage and temperature (PVT) corners and Monte Carlo simulations. The results show that by implementing the calibration it was possible to reduce the variability of the SNDR results, as well as increase worst corners results. |
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