Detalhes bibliográficos
| Resumo: | A Sigma-Delta Digital to Analog Converter (SDDAC) is a system that converts an input digital signal into an analog one by making use of oversampling and sigma-delta modulation to increase the Signal-to-Quantization-Noise Ratio (SQNR). This thesis studies architectures of SDDACs to drive a Voltage Controlled Crystal Os- cillator (VCXO) in a double Phase-Locked Loop (PLL) system. The goal is to achieve a phase noise due to the SDDAC that is lower than the intrinsic VCXO phase noise. The VCXO has a free-run frequency of 122.88 MHz, and its output is also used for a sampling clock in the digital filter that precedes the SDDAC. This study will allow choosing the best SDDAC that satisfies the noise requirements. The studies are done by discrete time simulations on a developed tool that consists of high-level models of SDDACs that take into consideration many digital sigma-delta modula- tor architectures, and a variety of non-idealities and noise on a current steering Digital-to- Analog Converter (DAC) and on a gm-C low-pass reconstruction filter. The developed tool is presented in this thesis, as is a study of the phase noise due to SDDACs is shown as a proof of concept. This work also includes the design of some of the main analog blocks in a 10-bit 122.88 MHz current steering DAC in 130nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. |
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| Autores principais: | Lopes, Miguel António Soldado |
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| Assunto: | Sigma-Delta Modulation Digital to Analog Conversion Voltage-Controlled Crystal Oscillator Phase Noise High-Level Modelling Current Steering Digital-to-Analog Conversion |
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| Ano: | 2022 |
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| País: | Portugal |
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| Tipo de documento: | dissertação de mestrado |
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| Tipo de acesso: | acesso aberto |
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| Instituição associada: | Universidade Nova de Lisboa |
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| Idioma: | inglês |
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| Origem: | Repositório Institucional da UNL |
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